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16 channel , 14- bit, 65 msps, serial lvds, 1.8 v adc data sheet AD9249 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication o r otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features low power 16 adc ch annels integrated into 1 packag e 58 mw per channel at 65 msps with scalable power options 3 5 mw per channel at 20 msps snr : 7 5 db fs (to nyquist) ; sfdr: 90 dbc (to nyquist) dnl: 0. 6 lsb (typical); inl: 0.9 lsb (typical) crosstalk, w orst a dj acent c hannel, 10 mhz, ? 1 dbfs : ? 90 db typ ical serial lvds (ansi - 644, default) low power, reduced signal option (similar to ieee 1596.3) data and frame clock outputs 650 mhz full power analog bandwidth 2 v p - p input voltage range 1.8 v supply operation serial port control flexible bit orientation built in and custom digital test pattern generation programmable clock and data alignment power - down and s tandby mode s applications medical imaging communications receivers multichannel d ata a cquisition general description the AD9249 is a 16 - c hannel , 1 4 - bit, 65 msps analog - to - digital converter (adc) with an on - chi p sample - and - hold circuit that is designed for low cost, low power, small size, and ease of use. the device operates at a conversion rate of up to 65 msps and is optimized for outstanding dynamic perf ormance and low power in applications where a small package size is critical. the adc requires a single 1.8 v power supply and an lvpecl - / cmos - /lvds - compatible sample rate clock for full performance operation. no external reference or driver components ar e required for many applications. the AD9249 automatically multiplies the sample rate clock for the appropriate lvds serial data rate. d ata clock output s (dco 1, dco 2 ) for capturing data on the output and frame clock output s (fco 1, fco 2 ) for signaling a new output byte are provided. individual channel power - down is supported, and the device typically consumes less than 2 mw when all channels are disabled. simplified functiona l block diagram figure 1. the adc contains several features designed to maximize flexibility and minimize system cos t , such as programmable clock and data alignment and programmable digital test pattern generation. the available digital test patterns include built - in deterministic and pseudorandom patterns, along with custom user - defined test patterns entered via the serial port interface (spi). the AD9249 i s available in a n rohs - compliant , 1 44 - ball csp - bga . it is specified over the industrial temperature range of ?40 c to + 85 c. this product is protected by a u.s. patent. product highlights 1. small footprint. sixteen adcs are contained in a small, 10 mm 10 mm package . 2. l ow p ower . 3 5 mw/c hannel at 20 msps with s calable power o ptions . 3. ease of use. d ata clo ck output s ( dco 1, dco 2 ) operate at frequencies of up to 455 mhz and support double data rate (ddr) operation. 4. user flexibility. spi control offers a wide range of flexible features to meet specific system requirements. AD9249 avdd pdwn data rate multiplier serial port interface fco+1, fco+2 fco?1, fco?2 dco+1, dco+2 dco?1, dco?2 ref select vref vcm1, vcm2 1.0v sync sense rbias1, rbias2 gnd csb1, csb2 clk+ clk? sdio/ dfs sclk/ dtp drvdd vin+a1 vin?a1 adc serial lvds d+a1 d?a1 14 vin+a2 vin?a2 adc serial lvds d+a2 d?a2 14 vin+h1 vin?h1 adc serial lvds d+h1 d?h1 14 vin+h2 vin?h2 adc serial lvds d+h2 d?h2 14 11536-200
AD9249 data sheet rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 simplifi ed functional block diagram ........................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 spec ifications ..................................................................................... 4 dc specifications ......................................................................... 4 ac specifications .......................................................................... 5 digital specifications ................................................................... 6 switching specifications .............................................................. 7 timi ng specifications .................................................................. 9 absolute maximum ratings .......................................................... 10 thermal characteristics ............................................................ 10 esd c aution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 13 equivalent circuits ......................................................................... 16 theory o f operation ...................................................................... 17 analog input considerations .................................................... 17 voltage reference ....................................................................... 18 clock input considerations ...................................................... 19 po wer dissipation and power - down mode ........................... 21 digital outputs and timing ..................................................... 21 built - in output test modes .......................................................... 25 output test modes ..................................................................... 25 serial por t interface (spi) .............................................................. 26 configuration using the spi ..................................................... 26 hardware interface ..................................................................... 27 configuration without the spi ................................................ 27 spi accessible features .............................................................. 27 memory map .................................................................................. 28 reading the memory map register table ............................... 28 memory map register table ..................................................... 29 me mory map register descriptions ........................................ 32 applications information .............................................................. 34 design guidelines ...................................................................... 34 power and ground recommendations ................................... 34 board layout considerations ................................................... 34 clock stability considerations ................................................. 35 vcm ............................................................................................. 35 reference decoupling ................................................................ 35 spi port ........................................................................................ 35 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 36 revision history 10 /13 revision 0: initial version
data sheet AD9249 rev. 0 | page 3 of 36 functional block dia gram figure 2. AD9249 avdd pdwn data rate multiplier serial port interface fco+1, fco+2 fco?1, fco?2 dco+1, dco+2 dco?1, dco?2 ref select vref vcm1, vcm2 1.0v sync sense rbias1, rbias2 gnd csb1, csb2 clk+ clk? sdio/ dfs sclk/ dtp drvdd vin+a1 vin?a1 adc serial lvds d+a1 d?a1 14 vin+a2 vin?a2 adc serial lvds d+a2 d?a2 14 vin+b1 vin?b1 adc serial lvds d+b1 d?b1 14 vin+b2 vin?b2 adc serial lvds d+b2 d?b2 14 vin+c1 vin?c1 adc serial lvds d+c1 d?c1 14 vin+c2 vin?c2 adc serial lvds d+c2 d?c2 14 vin+d1 vin?d1 adc serial lvds d+d1 d?d1 14 vin+d2 vin?d2 adc serial lvds d+d2 d?d2 14 vin+e1 vin?e1 adc serial lvds d+e1 d?e1 14 vin+e2 vin?e2 adc serial lvds d+e2 d?e2 14 vin+f1 vin?f1 adc serial lvds d+f1 d?f1 14 vin+f2 vin?f2 adc serial lvds d+f2 d?f2 14 vin+g1 vin?g1 adc serial lvds d+g1 d?g1 14 vin+g2 vin?g2 adc serial lvds d+g2 d?g2 14 vin+h1 vin?h1 adc serial lvds d+h1 d?h1 14 vin+h2 vin?h2 adc serial lvds d+h2 d?h2 14 11536-001
AD9249 data sheet rev. 0 | page 4 of 36 specifications dc specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, a in = ?1.0 dbfs, unless otherwise noted. table 1 . parameter 1 temp min typ max unit resolution 14 bits accuracy no missing codes full guaranteed offset error full 0 0. 24 0.8 % fsr offset matching full 0 0.2 4 0.7 % fsr gain error full ? 7.2 ? 3.5 + 0.2 % fsr gain matching full 0 1. 8 6.0 % fsr differential nonlinearity (dnl) full ? 0.9 0. 6 + 1.6 lsb integral nonlinearity (inl) full ? 3.0 0.9 + 3.0 lsb temperature drift offset error full ? 1.8 ppm/ c gain error full 3.6 ppm/ c internal voltage reference output voltage (1 v mode) full 0.98 1.0 1.01 v load regulation at 1.0 ma (v ref = 1 v) 25c 3 mv input resistance full 7.5 k input referred noise v ref = 1.0 v 25c 0.9 8 lsb rms analog inputs differential input voltage (v ref = 1 v) full 2 v p -p common - mode voltage full 0.9 v common - mode range full 0.5 1.3 v differential input resistance full 5.2 k differential input capacitance full 3.5 pf power supply avdd full 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 v i avdd full 395 429 ma i drvdd (ansi - 644 mode) full 118 124 ma i drvdd (reduced range mode) 25c 88 ma total power consumption total power dissipation ( 16 channels, ansi - 644 mode) full 924 995 mw total power dissipation ( 16 channels , reduced range mode) 25c 869 mw power - down dissipation 25c 2 mw standby dissipation 2 25c 199 mw 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for information about how these tests were completed. 2 c ontrolled via the spi.
data sheet AD9249 rev. 0 | page 5 of 36 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, a in = ?1.0 dbfs, unless otherwise noted. table 2 . parameter 1 temp min typ max unit signal - to - noise ratio (snr) f in = 9.7 mhz 25c 75.4 dbfs f in = 19.7 mhz full 74.4 75.3 dbfs f in = 48 mhz 25c 7 4. 7 dbfs f in = 69.5 mhz 25c 74 .4 dbfs f in = 118 mhz 25c 7 2 .8 dbfs f in = 139.5 mhz 25c 7 2.2 dbfs signal - to - noise and distortion ratio (sinad) f in = 9.7 mhz 25c 75.4 dbfs f in = 19.7 mhz full 74.0 75.3 dbfs f in = 48 mhz 25c 74.7 dbfs f in = 69.5 mhz 25c 74.4 dbfs f in = 118 mhz 25c 72.6 dbfs f in = 139.5 mhz 25c 71.8 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 12.2 bits f in = 19.7 mhz full 12.0 12.2 bits f in = 48 mhz 25c 12 .1 bits f in = 69.5 mhz 25c 12.1 bits f in = 118 mhz 25c 11.8 bits f in = 139.5 mhz 25c 11. 6 bits spurious - free dynamic range (sfdr) f in = 9.7 mhz 25c 95 dbc f in = 19.7 mhz full 85 93 dbc f in = 48 mhz 25c 94 dbc f in = 69.5 mhz 25c 92 dbc f in = 118 mhz 25c 83 dbc f in = 139.5 mhz 25c 8 2 dbc worst harmonic (second or third) f in = 9.7 mhz 25c ? 98 dbc f in = 19.7 mhz full ? 93 ? 85 dbc f in = 48 mhz 25c ? 94 dbc f in = 69.5 mhz 25c ? 92 dbc f in = 118 mhz 25c ? 83 dbc f in = 139.5 mhz 25c ? 8 2 dbc worst other (excluding second or third) f in = 9.7 mhz 25c ? 9 5 dbc f in = 19.7 mhz full ? 9 6 ? 86 dbc f in = 48 mhz 25c ? 94 dbc f in = 69.5 mhz 25c ? 92 dbc f in = 118 mhz 25c ? 90 dbc f in = 139.5 mhz 25c ? 90 dbc two - tone intermodulation distortion (imd) ain1 and ain2 = ?7.0 dbfs f in1 = 30 .1 mhz, f in2 = 32 .1 mhz 25c 9 2 dbc crosstalk , worst adjacent channel 2 25c ? 90 db crosstalk , wo rst adjacent channel overrange condition 3 25c ? 85 db analog input bandwidth, full power 25c 650 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 1 0 mhz , with ? 1.0 dbfs analog input on one channel and no input on the adjacent channel. 3 overrange condition is defin ed as 3 db above input full scale .
AD9249 data sheet rev. 0 | page 6 of 36 digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, a in = ?1.0 dbfs, unless otherwise noted. table 3 . parameter 1 temp min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 0.2 3.6 v p -p input voltage range full gnd ? 0.2 avdd + 0.2 v input common - mode voltage full 0.9 v input resistance (differential) 25c 15 k input capacitance 25c 4 pf logic inputs (pdwn, sync, sclk) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 30 k input capacitance 25c 2 pf logic input s (csb 1, csb2 ) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k input capacitance 25c 2 pf logic input (sdio) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k input capacitance 25c 5 pf logic output (sdio) 3 logic 1 voltage (i oh = 800 a) full 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 v digital outputs (dx 1, d x2 ), ansi - 644 logic compliance lvds differential output voltage (v od ) full 2 81 350 4 22 mv output offset voltage (v os ) full 1.1 2 1.2 2 1.38 v output coding (default) twos complement digital outputs ( dx 1, d x2 ), low power, reduced signal option logic compliance lvds differential output voltage (v od ) full 150 20 1 250 mv output offset voltage (v os ) full 1.1 2 1.2 2 1.38 v output coding (default) twos complement 1 see the an - 835 application note , understanding high sp eed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 s pecified for lvds and lvpecl only. 3 s pecified for 13 sdio/ dfs pins sharing the same connection.
data sheet AD9249 rev. 0 | page 7 of 36 switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, a in = ?1.0 dbfs, unless otherwise noted. table 4 . parameter 1 , 2 symbol temp min typ max unit clock 3 input clock rate full 10 520 mhz conversion rate full 10 65 msps clock pulse width high t eh full 7.69 ns clock pulse width low t el full 7.69 ns output parameters 3 propagation delay t pd full 1.5 2.3 3.1 ns rise time (20% to 80%) t r full 300 ps fall time (20% to 80%) t f full 300 ps fco1, fco2 propagation delay t fco full 1.5 2.3 3.1 ns dco1, dco2 propagation delay 4 t cpd full t fco + (t sample /28 ) ns dco1, dco2 to data delay 4 t data full (t sample /28 ) ? 300 (t sample /28 ) (t sample /28 ) + 300 ps dco1, dco2 to fco 1, fco 2 delay 4 t frame full (t sample /28 ) ? 300 (t sample /28 ) (t sample /28 ) + 300 ps data to data skew t data - max ? t data - min full 50 200 ps wake - up time (standby) 25c 35 s wake - up time (power - down) 5 25c 375 s pipeline latency full 16 clock cycles aperture aperture delay t a 25c 1 ns aperture uncertainty (jitter) t j 25c 135 f s rms out -of - range recovery time 25c 1 clock cycles 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 measured on standard fr - 4 material. 3 adjustable us ing the spi. 4 t sample /28 is ba sed on the number of bits, divided by 2, because the delays are based on half duty cycles. t sample = 1/f s ample . 5 wake - up time is defined as the time required to return to normal operation from power - down mode.
AD9249 data sheet rev. 0 | page 8 of 36 timing diagrams refer to the memory map register descriptions section for spi register setting of output mode . figure 3 . wordw ise ddr, 1 fr ame, 14 - bit output mode (default) figure 4 . wordw ise ddr, 1 frame, 12 - bit output mode dco?1, dco?2 dco+1, dco+2 fco?1, fco?2 fco+1, fco+2 d?x1, d?x2 d+x1, d+x2 vinx1, vinx2 clk? clk+ msb n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d0 n ? 17 d1 n ? 17 d12 n ? 16 msb n ? 16 n ? 1 t a t eh t cpd t fco t pd t data t frame t el n 1 1536-002 vinx1, vinx2 clk? clk+ msb n ? 17 d10 n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 d0 n ? 17 d10 n ? 16 msb n ? 16 n ? 1 n t da t a t frame t fco t pd t cpd t eh t a t el 1 1536-003 dco?1, dco?2 dco+1, dco+2 fco?1, fco?2 fco+1, fco+2 d?x1, d?x2 d+x1, d+x2
data sheet AD9249 rev. 0 | page 9 of 36 timing specification s table 5 . parameter description limit unit sync timing requirements t ssync sync to rising edge of clk+ setup time 0.24 ns typ t hsync sync to rising edge of clk+ hold time 0.40 ns typ spi timing requirements see figure 50 t ds setup time between the data and the rising edge of sclk 2 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb 1/csb2 and sclk 2 ns min t h hold time between csb 1/csb2 and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 50) 10 ns min t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 50) 10 ns min sync timing diagram figure 5 . sync input timing requirements sync clk+ t hsync t ssync 1 1536-004
AD9249 data sheet rev. 0 | page 10 of 36 absolute maximum rat ings table 6 . parameter rating electrical avdd to gnd ? 0.3 v to +2.0 v drvdd to gnd ? 0.3 v to +2.0 v digital outputs ( d x1 , d x 2 , dco 1 , dco 2 , fco 1 , fco 2 ) to gnd ? 0.3 v to +2.0 v clk+, clk? to gnd ? 0.3 v to +2.0 v v in x 1, v in x2 to gnd ? 0.3 v to +2.0 v sclk/dtp, sdio/ dfs , csb 1, csb2 to gnd ? 0.3 v to +2.0 v sync, pdwn to gnd ? 0.3 v to +2.0 v rbias 1, rbias2 to gnd ? 0.3 v to +2.0 v vref, vcm 1, vcm2 , sense to gnd ? 0.3 v to +2.0 v environmental operating temperature range (ambient) ? 40 c to + 85c maximum junction temperature 150c lead te mperature (soldering, 10 sec) 300c storage temperature range (ambient) ? 65c to +150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characterist ics typical ja is specified for a 4 - layer pcb with a solid ground plane. a irflow improves heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces ja . table 7 . thermal resistance (simulated) package type airflow velocit y (m/sec) ja 1, 2 jt 1, 2 unit 144 - ball , 10 mm 10 mm csp - bga 0 30.2 0.13 c/w 1 per jedec 51 - 7, plus jedec 51 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). esd c aution
data sheet AD9249 rev. 0 | page 11 of 36 pin configuration and function description s figure 6. pin configuration table 8 . pin function descriptions pin no. mnemonic description c10, d1 to d3, d10, e3, e5 to e8, f1 to f3, f5 to f8, g3, g5 to g8, h3, h5 to h8, h10, j3, j10, k5 to k8 gnd ground . d4 to d9, e4, e9, f4, f9, g4, g9, h4, h9, j4 to j9 avdd 1.8 v analog supply. k3, k4, k9, k10 drvdd 1.8 v digital output driver supply. e1, e2 clk?, clk+ input clock complement, input clock true. g12, g11 d ? a1 , d+a1 bank 1 digital output complement, bank 1 digital output true . h12, h11 d ? a2 , d+a2 bank 2 digital output complement, bank 2 digital output true . j12, j11 d ? b1 , d+b1 bank 1 digital output complement, bank 1 digital output true . k12, k11 d ? b2 , d+b2 bank 2 digital output complement, bank 2 digital output true l12, l11 d ? c1 , d+c1 bank 1 digital output complement, bank 1 digital output true . vin?g2 vin+g2 vin?g1 vin?f2 vin?f1 vin?e2 vin?e1 vin?d2 vin?d1 vin?c2 vin+c1 vin?c1 vin?h1 vin+h1 vin+g1 vin+f2 vin+f1 vin+e2 vin+e1 vin+d2 vin+d1 vin+c2 vin+b2 vin?b2 vin?h2 vin+h2 sync vcm1 vcm2 vref sense rbias1 rbias2 gnd vin+b1 vin?b1 gnd gnd gnd avdd avdd avdd avdd avdd avdd gnd vin+a2 vin?a2 clk? clk+ gnd avdd gnd gnd gnd gnd avdd csb1 vin+a1 vin?a1 gnd gnd gnd avdd gnd gnd gnd gnd avdd csb2 sdio/dfs sclk/dtp d?h2 d+h2 gnd avdd gnd gnd gnd gnd avdd pdwn d+a1 d?a1 d?h1 d+h1 gnd avdd gnd gnd gnd gnd avdd gnd d+a2 d?a2 d?g2 d+g2 gnd avdd avdd avdd avdd avdd avdd gnd d+b1 d?b1 d?g1 d+g1 drvdd drvdd gnd gnd gnd gnd drvdd drvdd d+b2 d?b2 d?f2 d+f2 d+e2 d+e1 fco+1 dco+1 dco+2 fco+2 d+d2 d+d1 d+c1 d?c1 d?f1 d+f1 d?e2 d?e1 fco?1 dco?1 dco?2 fco?2 d?d2 d?d1 d+c2 d?c2 a b c d e f g h j k l m 1 2 3 4 5 6 7 8 9 10 11 12 AD9249 top view (not to scale) 1 1536-005
AD9249 data sheet rev. 0 | page 12 of 36 pin no. mnemonic description m12, m11 d ? c2 , d+c2 bank 2 digital output complement, bank 2 digital output true . m10, l10 d ? d1 , d+d1 bank 1 digital output complement, bank 1 digital output true . m9, l9 d ? d2 , d+d2 bank 2 digital output complement, bank 2 digital output true . m4, l4 d ? e1 , d+e1 bank 1 digital output complement, bank 1 digital output true . m3, l3 d ? e2 , d+e2 bank 2 digital output complement, bank 2 digital output true . m1, m2 d ? f1 , d+f1 bank 1 digital output complement, bank 1 digital output true . l1, l2 d ? f2 , d+f2 bank 2 digital output complement, bank 2 digital output true . k1, k2 d ? g1, d+g1 bank 1 digital output complement, bank 1 digital output true . j1, j2 d ? g2, d+g2 bank 2 digital output complement, bank 2 digital output true . h1, h2 d ? h1 , d+h1 bank 1 digital output complement, bank 1 digital output true . g1, g2 d ? h2 , d+h2 bank 2 digital output complement, bank 2 digital output true . m6, l6, m7, l7 dco? 1 , dco+ 1, dco? 2 , dco+ 2 data clock digital output complement, data clock digital output true. dco 1 is used to capture d x1 digital output data ; dco 2 is used to capture d x2 digital output data . m5, l5, m8, l8 fco? 1 , fco+ 1, fco ? 2 , fco+ 2 frame clock digital output complement, frame clock digital output true. fco 1 frame s d x1 digital output data; fco 2 frame s d x2 digital output data . f12 sclk/dtp serial clock (sclk)/digital test pattern (dtp). f11 sdio/dfs serial data input/output (sdio)/data format select (dfs). e10, f10 csb 1, csb2 chip select bar. csb1 enables/disables spi for eight channels in bank 1; csb2 enables/disables spi for eight channels in bank 2 . g10 pdwn power - down. e12, e11 v in ? a1, v in +a1 analog input complement, analog input true . d12, d11 v in ? a2, v in +a2 analog input complement, analog input true . c12, c11 v in ? b1, v in +b1 analog input complement, analog input true . b12, b11 v in ? b2, v in +b2 analog input complement, analog input true . a12, a11 v in ? c1, v in +c1 analog input complement, analog input true . a10, b10 v in ? c2, v in +c2 analog input complement, analog input true . a9, b9 v in ? d1, v in +d1 analog input complement, analog input true . a8, b8 v in ? d2, v in +d2 analog input complement, analog input true . a7, b7 v in ? e1, v in +e1 analog input complement, analog input true . a6, b6 v in ? e2, v in +e2 analog input complement, analog input true . a5, b5 v in ? f1, v in +f1 analog input complement, analog input true . a4, b4 v in ? f2, v in +f2 analog input complement, analog input true . a3, b3 v in ? g1, v in +g1 analog input complement, analog input true . a1, a2 v in ? g2, v in +g2 analog input complement, analog input true . b1, b2 v in ? h1, v in +h1 analog input complement, analog input true . c1, c2 v in ? h2, v in +h2 analog input complement, analog input true . c8, c9 rbias 1, rbias2 sets analog current b ias. connect each rbias x pin to a 10 k (1% tolerance) resistor to ground. c7 sense reference mode selection. c6 vref voltage reference input/output. c4, c5 vcm 1, vcm2 analog output voltage at m id s upply. sets the common mode of the analog inputs , external to the adc, as shown in figure 35 and figure 36. c3 sync digital input; synchronizing input to c l ock d ivider. this pin is internally pulled to ground by a 30 k resistor .
data sheet AD9249 rev. 0 | page 13 of 36 typical performance characteristics figure 7. single - tone 32k fft with f in = 9.7 mhz, f sample = 65 msps figure 8. single - tone 32k fft with f in = 1 9.7 mhz, f sample = 65 msps figure 9. single - tone 32k fft with f in = 48 mhz, f sample = 65 msps figure 10 . single - tone 32k fft with f in = 69.5 mhz, f sample = 65 msps figure 11 . single - tone 32k fft with f in = 118 mhz, f sample = 65 msps figure 12 . single - tone 32k fft with f in = 139.5 mhz, f sample = 65 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 9.7mhz snr = 75.47dbfs sinad = 74.45dbc sfdr = 96.6dbc 1 1536-106 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 19.7mhz snr = 75.39dbfs sinad = 74.35dbc sfdr = 95.8dbc 1 1536-107 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 48mhz snr = 74.78dbfs sinad = 73.75dbc sfdr = 96.6dbc 1 1536-108 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 69.5mhz snr = 74.41dbfs sinad = 73.37dbc sfdr = 92.3dbc 1 1536-109 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 118mhz snr = 72.86dbfs sinad = 71.55dbc sfdr = 83.3dbc 1 1536- 1 10 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 139.5mhz snr = 72.22dbfs sinad = 70.84dbc sfdr = 82.7dbc 1 1536- 11 1
AD9249 data sheet rev. 0 | page 14 of 36 figure 13 . single - tone 32k fft with f in = 139.5 mhz, f sample = 65 msps , c lock divider = 4 figure 14 . snr/sfdr vs. input amplitude ; f in = 9.7 mhz, f sample = 65 msps figure 15 . two tone fft, f in = 30 .1 mhz and 32 .1 mhz , f sample = 65 msps figure 16 . two - ton e sfdr/imd3 vs. input amplitude ; f in1 = 30 .1 mhz , f in2 = 32 .1 mhz, f sample = 65 msps figure 17 . snr/sfdr vs. f in ; f sample = 65 msps figure 18 . snr/sfdr vs. temperature ; f in = 9.7 mhz, f sample = 65 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 139.5mhz snr = 72.74dbfs sinad = 71.45dbc sfdr = 84dbc 1 1536- 1 12 120 100 80 60 40 20 0 ?20 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) snr (db) sfdr (dbc) snrfs (dbfs) sfdr (dbfs) 1 1536- 1 13 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) a in = ?7dbfs f in = 30.1mhz, 32.1mhz imd2 = ?95.4dbc imd3 = ?95.4dbc sfdr = 93.0dbc f2 ? f1 f1 + f2 2f1 + f2 2f1 ? f2 f1 + 2f2 2f2 ? f1 1 1536- 1 14 0 ?120 ?100 ?80 ?60 ?40 ?20 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) ?sfdr (dbc) imd3 (dbc) ?sfdr (dbfs) imd3 (dbfs) 1 1536- 1 15 110 100 90 80 70 60 50 40 30 20 10 0 0 50 100 150 200 250 300 350 400 450 500 snr/sfdr (dbfs/dbc) input frequency (mhz) sfdr (dbc) snrfs (dbfs) 1 1536- 1 16 105 65 70 75 80 85 90 95 100 ?40 ?15 10 35 60 85 snr/sfdr (dbfs/dbc) temperature (c) sfdr (dbc) 1 1536- 1 17 snrfs (dbfs)
data sheet AD9249 rev. 0 | page 15 of 36 figure 19 . inl ; f in = 9.7 mhz, f sample = 6 5 msps figure 20 . dnl ; f in = 9.7 mhz, f sample = 6 5 msps figure 21 . input referred noise histogram ; f sample = 65 msps figure 22 . snr/sfdr vs. sample rate ; f in = 9.7 mhz, f sample = 65 msps figure 23 . snr/sfdr vs. sample rate ; f in = 1 9.7 mhz, f sample = 65 msps 0.8 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 16000 14000 12000 10000 8000 6000 4000 2000 inl (lsb) output code 1 1536- 1 18 0.8 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 16000 14000 12000 10000 8000 6000 4000 2000 dnl (lsb) output code 1 1536- 1 19 900000 800000 700000 600000 500000 400000 300000 200000 100000 0 number of hits output code n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 0.98 lsb rms 1 1536-120 110 60 65 70 75 80 85 90 95 100 105 20 80 70 60 50 40 30 snr/sfdr (dbfs/dbc) sample rate (msps) snrfs (dbfs) sfdr (dbc) 1 1536-122 110 60 65 70 75 80 85 90 95 100 105 20 80 70 60 50 40 30 snr/sfdr (dbfs/dbc) sample rate (msps) snrfs (dbfs) sfdr (dbc) 1 1536-123
AD9249 data sheet rev. 0 | page 16 of 36 equivalent circuits fi gure 24 . equivalent analog input circuit figure 25 . equivalent clock input circuit figure 26 . equivalent sdio/ dfs input circuit figure 27 . equivalent digital output circuit figure 28 . equivalent sclk/dtp, sync , and pdwn input circuit figure 29 . equivalent rbias x and vcm x circuit figure 30 . equivalent csb x input circuit figure 31 . equivalent vref circuit a vdd vinx1, vinx2 1 1536-034 clk+ clk? 0.9v 15k? 10? 10? 15k? a vdd a vdd 1 1536-035 30k? 30k? sdio/dfs 350? avdd 11536-036 dr vdd drgnd d?x1, d?x2 d+x1, d+x2 v v v v 1 1536-037 350? a vdd 30k? sclk/dt p , sync, and pdwn 1 1536-038 rbias1, rbias2 and vcm1, vcm2 375? avdd 11536-039 csb1, csb2 350? avdd 30k? 11536-040 vref a vdd 7.5k? 375? 1 1536-041
data sheet AD9249 rev. 0 | page 17 of 36 theory of operation the AD9249 is a multistage, pipelined adc . each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outputs from each stage are combined into a final 14 - bit result in the digital correction logic. the serializer trans mits this converted data in a 14 - bit output. the pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, c onsists of a low resolution fl ash adc connected to a switched capacitor dac and an interstage residue amplifier (for example, a multiplying digital - to - analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac ou tput and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects err ors, and passes the data to the output buffers. the data is then serialized and aligned to the frame and data clocks. analog input conside rations the analog input to the AD9249 is a differential s witched capacitor circuit designed for processing differential input signals. this circuit can support a wide common - mode range while maintaining excellent performance. by using an input common - mode voltage of midsu pply, users can minimize signal dependent errors and achieve optimum performance. figure 32 . switched capacitor input circuit the clock signal alternately switches the input circuit between sample mode and hold mode (see figure 32 ). when the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small resistor , in series with e ach input , can help reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and , therefore , achieve the maximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. place e ither a differential capacitor or two single - ended capacitors on the inpu ts to provide a matching passive network. this configuration ultimately creates a low - pass filter at the input to limit unwanted broadband noise. see the an - 742 application note , frequency domain resp onse of switched - capacitor adcs ; the an - 827 application note , a resonant approach to interfacing amplifiers to switched - capacitor adcs ; and the analog dialogue article transformer - coupled front - end for wideband a/d converters (volume 39, april 2005) for more information . in general, the precise values var y, depend ing on the application. input common mode the analog inputs of the AD9249 are not internally dc biased. therefore, in ac - coupled applications, the user must provide this bias externally. f or optimum performance , set the device so that v cm = av dd /2 . however, the device can function over a wider range with reasonable performance, as shown in figure 33. an on - chip , common - mode voltage reference is includ ed in the design and is available at the vcm x pin. decouple the vcm x pin to ground using a 0.1 f capacitor, as described in the applications information section. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the AD9249 , the largest available input span is 2 v p - p. figure 33 . snr/sfdr vs. common - mode voltage, f in = 9.7 mhz, f sample = 6 5 msps s s h c par c sample c sample c par v i n? x h s s h v i n+ x h 11536-042 110 20 30 40 50 60 70 80 90 100 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 snr/sfdr (dbfs/dbc) v cm (v) snrfs (dbfs) sfdr (dbc) 1 1536-133
AD9249 data sheet rev. 0 | page 18 of 36 differential input configurations there are several ways to drive the AD9249 , either actively or passively. however, optimum performance is achieved by driving the analog input s differentially. using a differential double balun configuration to drive the AD9249 provides excellent perfor mance and a flexible interface to the adc (see figure 35 ) for baseband applications . similarly , differential trans former coupling also provides excellent performance (see figure 36) . b ecause the noise performance of most amplifiers is not adequ ate to achieve the true performance of the AD9249 , use of these passive configurations is recom mended where ver possible . regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. it is recommended that the AD9249 input s not be driven single - ended. voltage reference a stable and accurate 1.0 v voltage reference is built into the AD9249 . configure vref using either the internal 1.0 v reference or an externally applied 1.0 v reference voltage. the various reference modes are summarized in the internal reference connection section and the external reference operation section . bypass t he vref pin to ground e xternally , using a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. internal reference connection a comparator within the AD9249 detects the potential at the sense pin and configures the reference into two possible modes, which are summarized in table 9 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 34 ), setting vref to 1.0 v. table 9 . reference configuration summary selected mode sense voltage (v) resulting v ref (v) resulting differential span (v p - p) fixed internal reference gnd to 0.2 1.0 internal 2.0 fixed external reference avdd 1.0 applied to external vref pin 2.0 figure 34 . i nternal reference configuration figure 35 . differential double balun input configuration for baseband applications figure 36 . differential tra nsformer coupled configuration for baseband applications vref sense 0.5v adc select logic 0.1f 1.0f vin?x1, vin?x2 vin+x1, vin+x2 adc core 1 1536-044 adc r 0.1f 0.1f 2v p-p vcm1, vcm2 c *c1 *c1 c r 0.1f 0.1f 0.1f 33? 200? 33? 33? 33? et1-1-i3 c c 5pf r *c1 is optional 11536-045 vin+x1, vin+x2 vin?x1, vin?x2 2v p-p r r *c1 *c1 is optional 49.9 0.1f adt1-1wt 1:1 z ratio adc *c1 c vcm1, vcm2 33? 33? 200? 0.1f 5pf 1 1536-046 vin?x1, vin?x2 vin+x1, vin+x2
data sheet AD9249 rev. 0 | page 19 of 36 if the internal reference of the AD9249 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 37 shows h ow the internal reference voltage is affected by loading. figure 37 . v ref error vs. load current external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac - teristics. figure 38 shows the typical drift characteristics of the internal reference in 1.0 v mode. figure 38 . ty pical v ref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 7.5 k? load (see figure 31 ). the internal buffer generates the positive and negative full - scale references for the adc core. there fore, limit the external reference to a maximum of 1.0 v. do not leave the sense p in floating. clock input consider ations for optimum performance, clock the AD9249 sample clock inputs, clk+ and clk?, with a differential signal. the signal is typically ac - coupled int o the clk+ and clk? pins via a transformer or capacitors. th ese pins are biased internally (see figure 25 ) and require no external bias. clock input options th e AD9249 has a flexible clock input structure. the clock in put can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal bei ng used, clock source jitter is of the utmost concern, as describ ed in the jitter considerations section. figure 39 and figure 40 show two preferred methods for clocking the AD9249 (at clock rates of up to 520 mhz prior to the internal clock divider). a low jit ter clock source is converted from a single - ended signal to a diff erential signal using either an rf transformer or an rf balun. the rf balun configuration is recommended for clock frequencies from 6 5 mhz to 520 mhz, and the rf transformer is recom - mende d for clock frequencies from 10 mhz to 200 mhz. the anti parallel schottky diodes across the transformer/balun secondary winding limit clock excursions into the AD9249 to approximately 0.8 v p - p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9249 while preserving the fast rise and fa ll times of the signal that are critical to achieving a low jitter performance. however, the diode capaci - tance comes into play at frequencies above 500 mhz. take c are when choosing the appropriate signal limiting diode. figure 39 . transformer - coupled differential clock (up to 200 mhz) figure 40 . balun - coupled differential clock ( 65 mhz to 520 mhz ) 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?5.0 0 3.0 2.5 2.0 1.5 1.0 0.5 v ref error (%) load current (ma) interna l v ref = 1v 1 1536-047 4 ?8 ?40 85 v ref error (mv) temperature (c) ?6 ?4 ?2 0 2 ?15 10 35 60 1 1536-048 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr 1 1536-049 0.1f 0.1f 0.1f clock input 0.1f 50? clk? clk+ schottky diodes: hsms2822 adc 1 1536-050
AD9249 data sheet rev. 0 | page 20 of 36 if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 41 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 - x / ad9516 - x / ad9517 - x clock drivers offer excellent jitter performance. figure 41 . differential pecl sample clock (up to 520 mhz ) a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 42 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 - x / ad9516 - x / ad9517 - x clock drivers offer excellent jitter performance. figure 42 . differential lvds sample clock (up to 520 mhz ) in some applications, it may be acceptable to drive the sample clock inputs with a single - ended 1.8 v cmos signal. in such applica tions , drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor (see figure 43 ). figure 43 . single - ended 1.8 v cmos input clock (up to 200 mhz) input clock divider the AD9249 contains an input clock divider with th e ability to divide the input clock by integer values from 1 to 8. the AD9249 clock divider can be synchronized using the external sync input. bit 0 and bit 1 of register 0x109 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the cl ock divider to reset to its initial state. this synchronization feature allows the clock dividers of multiple devices to be aligned to guarantee simultaneous input sampling . clock duty cycle typical high speed adcs use both clock edges to generate a vari e ty of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD9249 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the per - formance of the AD9249 . noise and distortion perform ance are nearly flat for a wide range of duty cycles with the dcs turned on . jitter o n the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates of less than 20 mhz, nominally. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency ( f a ) that is due only to aperture jitter ( t j ) is expressed by snr degradation = 20 log 10 ? ? ? ? ? ? ? ? j a t f 2 1 in this equation, the rms aperture jitter represents the root - sum - square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 44). figure 44 . ideal snr vs. input frequency and jitter 10 ? 0.1f 0.1f 0.1f 0.1f ? ? n? n? clk? clk+ clock input clock input adc ad951x pecl driver 1 1536-051 10 ? 0.1f 0.1f 0.1f 0.1f n? n? clk? clk+ adc clock input clock input ad951x lvds driver 1 1536-052 optional ? 0.1f 0.1f 0.1f ? 1 1 ?5(6,6725,6237,21$/ clk? clk+ adc v cc n? n? clock input ad951x cmos driver 1 1536-053 1 10 100 1000 16 b i t s 14 b i t s 12 b i t s 30 40 50 60 70 80 90 100 1 10 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps a n a l og i npu t f reque n cy (m h z) 10 bits 8 bits rms clock jitter requirement snr (db) 1 1536-054
data sheet AD9249 rev. 0 | page 21 of 36 treat t he clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9249 . s eparate the clock driver p ower supplies from the adc output driver supplies to avoid modulating the clock signal with dig ital noise. low jitter, crystal controlled oscillators are excellent clock sources. if another type of source generates the clock (by gating, dividing, or an other method ), ensure that it is retimed by the original clock at the last step. see the an - 501 application note , aperture uncertainty and adc system performance , and the an - 756 application note , sampled systems and the effects of clock phase noise and jitter , for more in depth information about jitter performance as it relates to adcs. power dissipation an d power - down mode as shown in figure 45 , the power dissipated by the AD9249 is p roportional to its sample rate and can be set to one of s everal power saving modes using register 0x100 , bits[2:0] . figure 45 . total power vs. f sample for f in = 9.7 mhz the AD9249 is placed in power - down mode either by the spi port or by asserting the pdwn pin high. in this state, the adc typically dissipates 2 mw. during power - down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the AD9249 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed tha t supply voltage. low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. the i nternal capacitors are discharged when the device enters power - down mode and then must be recharged w hen returning to normal operation. as a result, wake - up time is related to the time spent in power - down mode, and shorter power - down cycles result in proportionally shorter wake - up times. when using the spi port interface, the user can place the adc in pow er - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. see the memory map section for more details on using these features. digital outputs and timing the AD9249 differential outputs conform to the ansi - 64 4 lvds standard on default power - up. this can be changed to a low power, reduced signal option (similar to the ieee 1596.3 standard) via the spi. the lvds driver current is derived on chip and sets t he output current at each output equal to a nominal 3.5 m a. a 100 ? differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing (or 700 mv p - p differential) at the receiver. when operating in reduced range mode, the output current reduces to 2 ma. this results in a 200 mv swing (or 400 mv p - p differential) across a 100 ? termination at the receiver. the AD9249 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas for superior switchi ng performance in noisy environments. single point - to - point net topologies are recommended with a 100 ? termination resistor placed as near to the receiver as possible. if there is no far end receiver termination or there is poor differential trace routing , timing errors may result. to avoid such timing errors, it is recom - mended that the trace length be less than 24 inches , with all traces the same length. place the differential output traces as near to each other as possible . an example of the fco and data stream with proper trace length and position is shown in figure 46 . figure 47 shows an lvds output timing example in reduced range mode. figure 46 . lvds output timing example in ansi - 644 mode (default) figure 47 . l vds output timing example in reduced range mode 1.0 0.9 0.8 0.7 0.6 0.5 0.4 10 total power (w) sample rate (msps) 20 30 40 50 60 50msps setting 65msps setting 20msps setting 1 1536-145 40msps setting fco 500mv/div dco 500mv/div data 500mv/div 5ns/div 1 1536-056 fco 500mv/div dco 500mv/div data 500mv/div 5ns/div 1 1536-057
AD9249 data sheet rev. 0 | page 22 of 36 figure 48 shows a n example of the lvds output using the ansi - 644 standard (default) data eye and a time in terval error (tie) jitter histo gram with trace lengths of less than 24 inches on st andard fr - 4 material . figure 48 . data eye for lvds outputs in ansi - 644 mode with trace lengths of le ss t han 24 inches on standard fr - 4 material, external 100 ? far end termination only figure 49 shows an example of trace lengths exceeding 24 inches o n standard fr - 4 material. note that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is the responsibility of the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal termination (increasing the current) of all 16 outputs to drive longer trace lengths , which can be achieved by programming register 0x15. al though this option produces sharper rise and fall times on the data edges and is less prone to bit err ors, it also increases the power dissipation of the drvdd supply . figure 49 . data eye for lvds outputs in ansi - 644 m ode with trace lengths of greater t han 24 inches on standard fr - 4 material , external 100 ? far end termination only the default format of the output data is twos complement. table 10 shows an example of the output coding format . to change the output data format to offset binary , see the memory map section. data from each adc is serialized and provided on a separate channel in ddr mode. the data rate for each serial stream is equal to 14 b its times the sample clock rate , quantity divided by 2 , with a maximum of 455 mbps (14 bits 65 msps) /2 = 455 mbps. the lowest typical conversion rate is 10 msps. see the memory map section for details on enabling this feature. table 10 . digital output coding input (v) condition (v) offset binary output mode twos complement mode vin+ ? vin? < ?vref ? 0.5 lsb 00 0000 0000 0000 10 0000 0000 0000 vin+ ? vin? = ?vref 00 0000 0000 0000 10 0000 0000 0000 vin+ ? vin? = 0 10 0000 0000 0000 00 0000 0000 0000 vin+ ? vin? = +vref ? 1.0 lsb 11 1111 1111 1111 01 1111 1111 1111 vin+ ? vin? > +vref ? 0.5 lsb 11 1111 1111 1111 01 1111 1111 1111 0.5k 1.0k 1.5k 2.5k 2.0k 0 ?60ps ?40ps ?20ps 0ps 20ps 40ps 60ps 80ps tie jitter histogram (hits) 400 300 200 100 ?400 ?300 ?200 ?100 0 ?0.8ns 0.8ns ?0.6ns 0.6ns ?1.0ns 1.0ns ?0.4ns 0.4ns ?0.2ns 0.2ns 0ns eye diagram voltage (mv) eye: all bits uls: 7000:400354 1 1536-058 0.5k 1.0k 1.5k 2.5k 2.0k 0 ?60ps ?80ps ?40ps ?20ps 0ps 20ps 40ps 60ps 80ps tie jitter histogram (hits) 300 200 100 ?300 ?200 ?100 0 ?0.8ns 0.8ns ?0.6ns 0.6ns ?1.0ns 1.0ns ?0.4ns 0.4ns ?0.2ns 0.2ns 0ns eye diagram voltage (mv) eye: all bits uls: 7000:18200 1 1536-059
data sheet AD9249 rev. 0 | page 23 of 36 two output clock types are provided to assist in capturing data from the AD9249 . dco 1 and dco 2 clock the output data , and their frequency is equal to 7 the sample clock (clk ) rate for the default mode of operation. data is clocked out of the AD9249 and must be captured on the rising and falling edges of the dco that supports double data rate (ddr) capturing. dco1 is used to capture the dx1 (bank 1) data; dco2 is used to capture the dx2 (bank 2) data. fco 1 and fco2 signal the start of a new output byte , and the frequency is equal to the sample clock rate . fco1 frame s the dx1 (bank 1) data; fco2 frame s the dx2 (bank 2) data (see figure 3 and figure 4 ) . when the spi is used, the dco phase can be adjusted in 60 increments relative to one data cycle (30 relative to one dco cycle) . this enables the user to refine system timing margins , if required. the default dco 1 and dco 2 to output data edge timing, as shown in figure 3 , is 180 relative to one data cycle (90 relative to one dc o cycle) . a 12 - bit serial stream can also be initiated from the spi. this allows the user to implement and test compatibility to lower resolution systems. when changing the resolution to a 12 - bit serial stream, the data stream is shortened. see figure 4 for the 12- bit example. in default mode, as shown in figure 3 , the msb is first in the data output serial stream. this can be inverted so that the lsb is first in the data output serial stream by using the spi. there are 12 digital output test pattern o ptions available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing (see table 11 for the out put bit sequencing options that are available ) . some test patterns have two serial sequential words and can alternate in various ways, depending on the test pattern chosen. note that some patterns do not adhere to the data format select option. in addition , custom user - defined test patterns can be assigned in register 0x19, register 0x1a, register 0x1b, and register 0x1c. table 11 . flexible output test modes output test mode bit sequence (reg. 0x0d) pattern name digital output word 1 1 digital output word 2 1 subject to data format select 1 notes 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 0000 (12 - bit) n/a yes offset binary code shown 10 0000 0000 0000 (14 - bit) 0010 +full - scale short 1111 1111 1111 (12 - bit) n/a yes offset binary code shown 11 1111 1111 1111 (14 - bit) 0011 ? full - scale short 0000 0000 0000 (12 - bit) n/a yes offset binary code shown 00 0000 0000 0000 (14 - bit) 0100 checkerboard 1010 1010 1010 (12 - bit) 0101 0101 0101 (12 - bit) no 10 1010 1010 1010 (14 - bit) 01 0101 0101 0101 (14 - bit) 0101 pn sequence long 2 n/a n/a yes pn23 itu 0.150 x 23 + x 18 + 1 0110 pn sequence short 2 n/a n/a yes pn9 itu 0 .150 x 9 + x 5 + 1 0111 one - / zero - word toggle 1111 1111 1111 (12 - bit) 0000 0000 0000 (12 - bit) no 11 1111 1111 1111 (14 - bit) 00 0000 0000 0000 (14 - bit) 1000 user input register 0x19 to register 0x1a register 0x1b to register 0x1c no 1001 1 - /0 - bit toggle 1010 1010 1010 (12 - bit) n/a no 10 1010 1010 1010 (14 - bit) 1010 1 sync 0000 0011 1111 (12 - bit) n/a no 00 0000 0111 1111 (14 - bit) 1011 one bit high 1000 0000 0000 (12 - bit) n/a no pattern associated with the external pin 10 0000 0000 0000 (14 - bit) 1100 mixed frequency 1010 0011 0011 (12 - bit) n/a no 10 1000 0110 0111 (14 - bit) 1 n/a means not applicable. 2 all test mode options except pn sequence short and pn sequence long can support 12 - bit to 14 - bit word lengths to verify data capture to the receiver.
AD9249 data sheet rev. 0 | page 24 of 36 the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 or 511 bits. refer to section 5.1 of the itu - t 0.150 (05/96) standard for a description of the pn sequence and how it is generated. the seed value is all 1s (see table 12 for the initial values). the output is a parallel representation of the serial pn9 sequence in msb - first format. the first output word is the first 14 bits of the pn9 sequence in msb aligned form. table 12 . pn sequence sequence initial value next three output samples (msb first) twos complement pn sequence short 0x1fe0 0x1df1, 0x3cc8, 0x294e pn sequence long 0x1fff 0x1fe0, 0x2001, 0x1c00 the pn sequence long patt ern produces a pseudorandom bit sequence that repeats itself every 2 23 ? 1 or 8,388,607 bits. refer to section 5.6 of the itu - t 0.150 (05/96) standard for a description of the pn sequence and how it is generated . the seed value is all 1s (see table 12 for the initial values) and the AD9249 inverts the bit stream with relation to the itu standard. the output is a parallel representation of the serial pn23 sequence in msb - first format. the first output word is the first 14 bits of the pn23 sequence in msb aligned form at . consul t the memory map section for information on how to change these additional digital output timing features through the spi. sdio/dfs pin for applications that do not require spi mode operation, the csb 1 and csb2 pin s are tied to avdd, and the sdio/dfs pin controls the output data format select as described in table 13. table 13 . output data format select pin settings dfs pin voltage output mode avdd twos c omplement gnd (default) offset b inary sclk/dtp p in the sclk/dtp pin can enable a single digital test pattern if it and the csb 1 and csb2 pin s are held high during device power - up . whe n sclk/dtp is tied to avdd, the adc channel outputs shif t out the following pattern: 10 0000 0000 0000. the fco 1, fco 2, dco 1 , and dco 2 pins function normally while all channels shift out the repeat able test pat tern. this pat tern allows the user to perform timing alignment adjustments among the fco 1, fco 2 , dco 1, dco 2 , and output data. th e sclk/ dtp pin has an internal 3 0 k? resistor to gnd. it can be left unconnected for normal operation . table 14 . digital test pattern pin settings selected dtp dtp voltage resulting d x x normal operation no connect normal operation dtp avdd 10 0000 0000 0000 additional and custom test patterns can also be observed when commanded from the spi port. consult the memory map section for information about the options that are available. csb 1 and csb2 pin s the csb 1 and csb2 pin s are tied to avdd for applications that do not require spi mode operation. tying csb 1 and csb2 high causes all sclk and sdio spi communication information to be ignored. csb1 selects/de selects spi circuitry affecting outputs d a1 to d h1 (bank 1). csb2 selects/de selects spi circuitry affecting outputs d a2 to d h2 (bank 2). it is recommended that csb1 and csb2 be controlled with the same signal ; that is, tie them together. in t his way, whether tying them to avdd or selecting spi functionality, both banks of adcs are controlled identically and are always in the same state. rbias 1 and rbias2 pin s to set the internal core bias current of the adc, place a 10.0 k ?, 1% tolerance resistor to ground at each of the rbias 1 and rbias2 pin s.
data sheet AD9249 rev. 0 | page 25 of 36 built - in output test modes the AD9249 includes a built - in test feature designed to enable verification of the integrity of each data output channel, as well as to facilitate board level debugging. vario us output test mode s are provided to place predictable values on the outputs of the AD9249 . output test modes the output test modes are described in table 11 and controlled by the output test mode bits at address 0x0d. when an output test mode is enabled, the analog section of the adc is disconnected from the digital back - end blocks and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bi t 5 of register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see the a n - 877 application note , interfacing to high speed adcs via spi .
AD9249 data sheet rev. 0 | page 26 of 36 serial port interfac e (spi) the AD9249 serial port interface (spi) allows the user to configure the converter for specific fu nctions or operations through a structured register space provided inside the adc. the spi offers the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which are docu - mented in the memory map sec tion. for general operational information, see the an - 877 application note , interfacing to high speed adcs via spi . spi information specific to the AD9249 is found in the AD9249 datasheet and takes precedence over the general information found in the an - 877 application note . configuration using the spi four pins define the spi of this adc : the sclk/dtp pin (sclk functionality) , the sdio/dfs pin (sdio functionality) , and the csb 1 and csb2 pin s (see table 15 ). sclk (a serial clock) is used to synchronize the read and write data presented from and to the adc. sdio (serial data input/output) serves a dual function that allows data to be sent to and read from the internal adc memory map registers. csb 1 and csb2 (chip select bar) are active low control s that enable or disable the read and write cycles. table 15 . serial port interface pins pin function sclk (sclk/dtp) serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio (sdio/dfs) serial data input/output. a dual - purpose pin that serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb 1, csb2 chip select bar. an active low control that gates the read and write cycles. csb1 enables/disables spi for eight channels in bank 1; csb2 enables/ disables spi for eight channels in bank 2 . the falling edge of csb 1 and/or csb2 , in conjunct ion with the rising edge of sclk, determines the start of the framing. for a n example of the serial timing and its definitions , see figure 50 and table 5 . other modes involving the csb 1 and csb2 pins are available. t o permanently enable the device , h old csb 1 and csb2 low indefi nitely; this is called streaming . csb 1 and csb2 can stall high between bytes to allow additional external timing. tie csb 1 and csb2 high to place spi functions in high impedance mode. this mode turns on any spi secondary pin functions. it is recommended that csb1 and csb2 be controlled with the same signal by tying them together. in this way , whether tying them to avdd or selecting spi functionality, both banks of adcs are controlled identically and are always in the same state. during an instruction phas e, a 16 - bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing th e serial port to both program the chip and read the contents of the on - chip memory. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. if the instruction is a readback op eration, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. input data registers on the rising edge of sclk , and output data transmit s on the falling edge. a fter the address infor mation passes to the converter requesting a read, the sdio line transitions from an input to an output within 1/2 of a clock cycle. this timing ensures that when the falling edge of the next clock cycle occurs, data can be safely placed on this serial line for the controller to read. all data is composed of 8 - bit words. data can be sent in msb first mode or in lsb - first mode. msb - first mode is the default on power - up and can be changed via the spi port configurat ion register. for more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi . figure 50 . serial port interface timing diagram don?t care don?t care don?t care don?t care sdio sclk csb1, csb2 t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 11536-060
data sheet AD9249 rev. 0 | page 27 of 36 hardware interface the pins described in table 15 comprise the physical interface between the user programming device and the serial port of the AD9249 . the sclk/dtp pin (sclk funct ionality) and the csb 1 and csb2 pin s function as inputs when using the spi interface. the sdio/ dfs pin (sdio functionality) is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note , micro - controller - based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb 1 and csb2 signal s , and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9249 to pr event these signals from transi tioning at the converter inputs during critical sampling periods. some pins serve a dual function when the spi interface is not being used. when the pins are strapped to drvdd or ground during device power - on, they are associated with a specific func tion. table 13 and table 14 describe the strappable functions supported on the AD9249 . configuration withou t the spi in applications that do not interface to the spi control registers, the sdio/dfs pin, the sclk/dtp pin, and the pdwn pin serve as standalone cmos - compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lin es for the output da ta format, output digital test pattern , and power - down feature control. in this mode, connect csb 1 and csb2 to avdd, which disa bles the serial port interface. when the device is in spi mode, the pdwn pin (if enabled) remains active. for spi control of powe r - down, set the pdwn pin to its inactive state (low) . spi accessible featu res table 16 provides a brief description of the general features that are accessible via the spi. these features are described further in the an - 877 application note , interfacing to high speed adcs via spi . the AD9249 device - specific features are described in detail in the memory map register descriptions section following table 17, the external memory map register table. table 16 . features accessible using the spi feature name description power mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs, set the clock divider, set the clock divider phase, and enable the sync function offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set the output mode output phase allows the user to set the output clock polarity adc resolution and speed grade allows s calable power consumption options based on resolution and speed grade selection
AD9249 data sheet rev. 0 | page 28 of 36 memory map reading the memory m ap register table each row in the memory map register table has eight bit locations. the memory map is divided into three sections: the chip con - figura tion registers (address 0x00 to address 0x02); the device index and transfer registers ( address 0x04, address 0x05 , and address 0xff); and the global adc function registers, including setup, control, and test (address 0x08 to address 0x109). the memory map register table (see table 17 ) lists the default hexadecimal value for each hexadecimal address shown. the column with the bit 7 (msb) heading is the msb of the binary 8 - bit representation . for example, ad dress 0x05, the device i ndex 1 register, has a hexadecimal default value of 0x3f. this means that in address 0x05, bits[7:6] = 0, and the remaining bits, bits[5: 0], = 1. this setting is the default channel index setting. the default value results in all specified adc channels receiving the next write command. for more information on this function and others, see the an - 877 application note , interfacing to high speed a dcs via spi. this application note details the functions controlled by register 0x00 to register 0xff. the remaining registers are documented in the memory map register descriptions section. open locations all address and bit locations that are not listed in table 17 are not currently supported for this device. write the u nused bits of a valid address location with 0s. writing to these locations is required only when some of the bits of an address location are valid (for example, address 0x05). do not write to an address location i f the entire address location is open or if the address is not listed in table 17 (for example, address 0x13) . default values after the AD9249 is reset (via bit 5 and bit 2 of address 0x00) , the registers are loaded with default values. the default values for the registers are listed in the default value ( hex) column of table 17 , the memory map register table. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. channel specific registers some channel setup functions can be programmed independent ly for each channel. in such cases, channel address locations are internally duplicated for each channel ; that is, each channel has its own set of registers . these registers and bits are designated in table 17 as local . access t hese local registers and bits by setting the appropriate data channel bits (a 1 , a2 through h1, h2 ) and the clock channel bits ( dco 1 , dco2 and fco 1, fco2), found in register 0x04 and register 0x05. if all the valid bits are set in register 0x04 and register 0x05 , the subsequent write to a local register affects the registers of all the data channels and the dco x /fco x clock channels. in a read cycle, set only one channel (a 1 , a2 through h 1, h 2 ) to read one local register . if all th e bits are set during a spi read cycle, the device returns the value for channel a 1 . registers and bits that are designated as global in table 17 are applicable to the channel features for which independent settings are not allowed ; thus , they affect the entire device . the settings in register 0x04 and register 0x05 do not affect the global registers and bits.
data sheet AD9249 rev. 0 | page 29 of 36 memory map the AD9249 uses a 3 - wire (bidirectional sdio) interface and 16 - bit addressing . t herefore, bit 0 and bit 7 in register 0x00 are set to 0, and bit 3 and bit 4 are set to 1. when bit 5 in register 0x00 is set hi gh, the spi enters a soft reset where all of the user regi sters revert to their default values and bit 2 is automatically cleared. table 17. memory map register table reg. addr. (hex) registe r name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments chip configuration registers 0x00 spi port configuration 0 = sd i o active lsb first soft reset 1 = 16- bit address 1 = 16- bit address soft reset lsb first 0 = sd i o active 0x18 n ibbles are mirrored such that a given register value yields the same function for either lsb first mode or msb first mode. 0x01 chip id (global) 8 - bit chip id, bits[7:0] ; 0x92 = the AD9249 , a 16- ch annel, 14- bit, 65 msps serial lvds read only ; 0x92 unique chip id used to differ - entiate devices . r ead only. 0x02 chip grade (global) open speed grade id, bits[6:4] ; 011 = 65 msps open open open open read only unique speed grade id used to differentiate g raded devices. read only. device index and transfer registers 0x04 device index 2 open open open open h 1 , h2 d ata c hannel s g 1 , g2 d ata c hannel s f 1 , f2 d ata c hannel s e1 , e2 d ata c hannel s 0x 0 f bits are set to determine which device on chip receives the next write command. the default is all devices on chip. 0x05 device index 1 open open dco 1, dco 2 clock c hannel s fco 1, fco 2 c lock channel s d 1, d2 d ata c hannel s c 1 , c2 data c hannel s b 1 , b2 d ata c hannel s a 1 , a2 d ata c hannel s 0x3f bits are set to determine which device on chip receives the next write command. the default is all devices on chip. 0xff transfer open open open open open open open initiate override 0x00 set s resolution/ sample rate override. global adc function registers 0x08 power modes (global) open open external power - down pin function ; 0 = full power - down , 1 = standby open open open internal power - down mode , bits[1:0] ; 00 = chip run 01 = full power - down 10 = standby 11 = digital reset 0x00 determines various generic modes of chip operation. 0x09 clock (global) open open open open open open open duty cycle stabilize r ; 0 = off 1 = on 0x01 turns duty cycle stabilizer on or off.
AD9249 data sheet rev. 0 | page 30 of 36 reg. addr. (hex) registe r name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x0b clock divide (global) open open open open open clock divide ratio , bits [2:0] ; 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 divide ratio is the value plus 1. 0x0c enhancement control open open open open open chop mode ; 0 = off 1 = on open open 0x00 enables/ disables chop mode. 0x0d test mode (local except for pn sequence resets) user input test mode , bits[7:6] ; 00 = single 01 = alternate 10 = single once 11 = alternate once (af fects user input test mode only; register 0x0d, bits[3:0] = 1000) reset pn long gen reset pn short gen output test mode, bits[3:0] (local) ; 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn 23 sequence 0110 = pn 9 sequence 0111 = one - /zero - word toggle 1000 = user input 1001 = 1 - /0 - bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency 0x00 when set, test data is placed on the output pins in place of normal data. 0x10 offset adjust (local) 8 - bit device offset adjustment, bits[7:0] (local) ; o ffset adjust in lsbs from +127 to ?128 (twos complement format) 0x00 device offset trim. 0x14 output mode open lvds - ansi/ lvds - ieee option ; 0 = lvds - ansi 1 = lvds - ieee reduced range link (global) ; see table 18 open open open output invert ; 0 = not inverted 1 = inverted (local) open output format ; 0 = offset binary 1 = twos comple - ment (default) (global) 0x01 configures outputs and format of the da ta. 0x15 output adjust open open output driver termination , bits[ 5:4 ] ; 00 = none 01 = 200 10 = 100 11 = 100 open open open fco x , dco x o utput drive (local) ; 0 = 1 drive 1 = 2 drive 0x00 determines lvds or other output properties. 0x16 output phase open input clock phase adjust, bits[6:4] ; (value is number of inp ut clock cycles of phase delay; see table 19 ) output clock phase adjust, bits[3:0] ; (s etting = 0000 to 1011; see table 20) 0x03 o n devices that use global clock divide, determines which phase of the divider output supplies the output clock. internal latching is unaffected. 0x18 v ref open open open open open input full - scale adjustment ; digital scheme, bits[2:0] ; 000 = 1.0 v p - p 001 = 1.14 v p - p 010 = 1.33 v p - p 011 = 1.6 v p - p 100 = 2.0 v p - p 0x04 digital adjust - ment of input full - scale voltage . does not affect analog voltage reference
data sheet AD9249 rev. 0 | page 31 of 36 reg. addr. (hex) registe r name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x19 user_patt1_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 1 lsb. 0x1a user_patt1_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 1 msb . 0x1b user_patt2_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 2 lsb. 0x1c user_patt2_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 2 msb. 0x21 serial output data control (global) lvds output lsb first wordwise ddr, one lane, bits[6:4] ; 100 = ddr , one lane pll low encode rate mode open serial output number of bits , bits[1:0] ; 01 = 14 bits 10 = 12 bits 0x41 serial stream control. default causes msb first and the native bit stream. 0x22 serial channel status (local) open open open open open open channel output reset channel power - down 0x00 p ower s down individual sections of a converter. 0x100 resolution/ sample rate override open resolution/ sample rate override enable resolution , bits[5:4] ; 01 = 14 bits 10 = 12 bits open sample rate , bits[2:0] ; 000 = 20 msps 001 = 40 msps 010 = 50 msps 011 = 65 msps 0x00 resolution/ sample rate override (requires transfer register , register 0xff). 0x101 user i/o control 2 open open open open open open open sdio pull - down 0x00 disables sdio pull - down. 0x102 user i/o control 3 open open open open vcm power - down open open open 0x00 vcm control. 0x109 sync open open open open open open sync next only enable sync 0x00
AD9249 data sheet rev. 0 | page 32 of 36 memory map register descriptions for additional information about functions controlled in register 0x00 to register 0xff, see the an - 877 application note , interfacing to high speed adcs via spi . device index (register 0x04 and register 0x05) there are certain features in the map that can be set independently for each channel, whereas other features apply globally to all channels (depending on context), regardless of which are selected. bits[3:0] in register 0x04 and register 0x05 select which individual data channels are affected. the output clock channels are selected in register 0x05 , as well. a smaller subset of the independent feature list can be applied to those devices. transfer (register 0xff) all registers except register 0x100 are updated the moment they are written. setting bit 0 = 1 in th e transfer register initializes the se ttings in the adc resolution/ sample rate override register (address 0x100). power modes (register 0x08) bits6 open bit 5 external power down pin function when set (bit 5 = 1) , the external pdwn pin initiates standby mode. when cleared (bit 5 = 0) , the external pdwn pin initiates full power - down mode. bits[4:2] open bits[1:0] internal power - down mode in normal operation (bits[1:0] = 00), all adc channels are active . in full power - down mode (bi ts[1:0] = 01), the digital data path clocks are disabled and the digital data path is reset. outputs are disabled . in standby mode (b its[1:0] = 10), the digital data path clocks and the outputs are disabled. during a digital reset (bits[1:0] = 11), all the digital data path clocks and the outputs (where applicable) on the chip are reset, except the spi port. note that the spi is always left under control of the user; that is, it is never automatically disabled or in reset (except by power - on reset). enhancement control (register 0x0c) bits3 open bit 2 chop mode for applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the AD9249 is a feature that can be enabled by setting bit 2 = 1 . in the frequency domain, chopping translates offsets and other low frequency noise to f clk /2, where they can be filtered. bits[1:0] open output mode (register 0x14) bit open bit 6 lvds ansi/lvds ieee option setting bit 6 = 1 chooses the lvds - ieee (reduced range) option. ( the default setting is lvds - ansi. ) as described in table 18, when either lvds - ansi mode or the lvds - ieee reduced range link is selected, the user can select the driver t ermination resistor in register 0x 15, bits[5:4] . the driver current is automatical ly selected to give the proper output swing. table 18 . lvds - ansi/lvds - ieee options lvds - ansi/ lvds - ieee option, bit 6 output mode output driver termination output driver current 0 lvds - ansi user selectable automatically selected to give proper swing 1 lvds -ieee reduced range link user selectable automatically selected to give proper swing bits[5:3] open bit 2 output invert setting bit 2 = 1 inverts the output bit stream. bit 1 open bit 0 output format by default, set ting bit 0 = 1 send s the data output in twos complement format. clearing this bit ( bit 0 = 0 ) changes the output mode to offset binary. output adjust (register 0x15) bits6 open bits54 output driver termination these bits allow the user to select the internal output driver termination resistor. bits[3:1] open bit 0 fco x, dco x output drive bit 0 of the output adjust register controls the drive strength on the lvds driver of the fco 1, fco 2, dco 1 , and dco 2 outputs only. the default value (bit 0 = 0) set s the drive to 1 . increase the drive to 2 by setting the appropriate channel bit in register 0x05 and then setting bit 0 = 1 . these features cannot be used with the output driver termination select ed . the termination selection takes prece dence over the 2 driver strength on fco 1, fco 2, dco 1 , and dco 2 when both the output driver termination and output drive are selected .
data sheet AD9249 rev. 0 | page 33 of 36 output phase (register 0x16) bit 7 open bits[6:4] input clock phase adjust when the clock divider (register 0x0b) is used, the applied clock is at a higher frequency than the internal sampling clock. bits[6:4] determine at which phase of the external clock the sampling occur s . this is applicable only when the clock divider is use d. it is prohibited to select a value for bits[6:4] that is greater than the value of bits[2:0], register 0x0b. see table 19 for more information. table 19 . input clock phase adjust options input clock phase adjust , bits [6:4] number of input clock cycles of phase delay 000 (default) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 bits[3:0] output clock phase adjust see table 20 for more information. table 20 . output clock phase adjust options output clock , phase adjust , bits [3:0] dco phase adjustment (degree s relative to d x edge) 0000 0 0001 60 0010 120 0011 (default) 180 0100 240 0101 300 0110 360 0111 420 1000 480 1001 540 1010 600 1011 660 resolution/sample rate override (register 0x100) this register is designed to allow the user to downgrade the device ( that is, establish lower power) for applications that do not require full sample rate . settings in this register are not initialized until bit 0 of the transfer register (register 0xff) is set to 1 . this function does not affect the s ample rate; it affects the maximum sample rate capability of the adc , as well as the resolution . user i/o control 2 (register 0x101) bits[7:1] open bit 0 sdio pull - down set bit 0 = 1 to disable the internal 30 k pull - down on the sdio/ dfs pin . this feature limit s loading when many devices are connected to the spi bus. user i/o control 3 (register 0x102) bits[7:4] open bit 3 vcm power - down set bit 3 = 1 to power down the internal vcm generator. this feature is used when applying an external reference. bits[2:0] open
AD9249 data sheet rev. 0 | page 34 of 36 applications informa tion design guidelines before starting the design and layout of the AD9249 as a system, it is recommended that t he designer become familiar with t hese guidelines, which describe the special circuit connections and layout requirements that are needed for certain pins. power and ground rec ommendations when connecting power to the AD9249 , it is recommended that two sep a rate 1.8 v supplies be used. use one supply for analog (avdd); use a separate supply for the digital outputs (drvdd). for both avdd and drvdd, use several different decoupling capacitors for both high and low frequencies. place these capacitors near the point of entry at the pcb level and near the pins of the device , with minimal trace length. a single pcb ground plane is typically sufficient when using the AD9249 . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. board layout c onsiderations for optimal performance, giv e special consideration to the AD9249 board layout. the high channel count and small footprint of the AD9249 create a dense configuratio n that must be managed for matters relating to crosstalk and sw itching noise. sources of coupling trace pairs interfere with each other by inductive coupling and capacitive coupling . use the following guidelines: ? inductive coupling is current induced in a trace by a changing magnetic field from an adjacent trace, caused by its changing current flow. mitigate t his effect by making traces orthogonal to each other whenever possible and by increasing the distance betwe en them. ? capacitive coupling is charge induced in a trace by the changing electr ic field of an adjacent trace. mitigate this effect by minimizing facing areas, increasing the distance between traces, or changing dielectric properties. ? through - vias are particularly good conduits for both types of coupling and must be used carefully. ? adjacent trace runs on the same layer may cause unbalanced coupling between channels. ? traces on one layer should be separated by a plane ( ac ground) from the traces on anothe r layer. significant coupling occurs through gaps in that plane, such as t he setback around through - vias. crosstalk between i nputs to avoid crosstalk between input s, consider the following guidelines : ? when routing inputs, sequentially alternate input chan nels on the top and bottom (or other layer) of the board. ? ensure that the top channels have no vias within 5 mm of any other input channel via . ? for b ottom channels , use a via - in - pad to m inimize top metal coupling between channels. ? avoid running input traces parallel with each other that are nearer than 2 mm apart . ? when possible , lay out traces orthogonal to each other and to any other traces that are not dc . ? second hand or indirect coupling may occur through non - related dc traces that bridge the distanc e between two traces or vias. coupling of digital output switching noise to analog inputs and clock to avoid the coupling of digital output switching noise to the analog inputs and the clock , use the following guidelines: ? vias on the outputs are a main con duit of no ise to the vias on the inputs. maintain 5 mm of separation between any output via and any input via. ? place the encode clock traces on the top surface. vias are not recommended in the clock traces . however, if they are required, ensure that there are no clock trace vias within 5 mm of any input via or output via. ? place o utput surface traces (not imbedded between planes) orthogonal to one another as much as possible. avoid parallel output to input traces within 2 mm. ? route digital output traces away from the analog input side of the board. ? coupling among outputs is not a critical issue, but separation between these high speed output pairs increases the noise margin of the signals and is good practice.
data sheet AD9249 rev. 0 | page 35 of 36 c lock s tability c onsiderations when powered on, the AD9249 enters an initialization phase where a n internal state machine sets up the biases and the registers for proper operation. during the initialization process , the AD9249 needs a stable clock. if the adc clock source is not present or not stable during adc power - up, the state machine is disrupted and the adc start s up in an unknow n state. t o correct this, re invoke an initiali zation sequence after the adc clock is stable by issuing a digital reset using r egister 0x08. in the default configuration (internal v ref , ac - coupled input) where v ref and v cm are supplied by the adc itself, a stable clock during power - up is sufficient. when v ref or v cm is supplied by an external source, it , too, must be stable at po wer - up. o therwise , a subsequent digital reset , using r egister 0x08 , is needed. the pseudo code sequence for a digital reset follows : spi_write (0x08, 0x03); # digital r eset spi_ write (0x08, 0x00); # normal o peration vcm decouple t he vcm x pin to ground with a 0.1 f capacitor. reference decoupling decouple the v ref pin externally to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port ensure that t he spi port is in active during periods when the full dynamic performance of the converter is required. because the sclk, csb 1, csb2 , and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9249 to prevent these signal s from transitioning at the con verter inputs during critical sampling periods.
AD9249 data sheet rev. 0 | page 36 of 36 outline dimensions figure 51 . 144 - ball chip scale package ball grid array [csp_bga ] (bc - 144 - 7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9249 b bc z -65 ? 40c to + 85c 144 - ball chip scale package ball grid array [csp_bga] bc - 144 -7 AD9249 bbc zrl7 -65 ? 40c to + 85c 144 - ball chip scale package ball grid array [csp_bga] bc - 144 -7 AD9249 -65 ebz evaluation board 1 z = rohs compliant part. compliant to jedec standards mo-275-eeab-1. 1 1-18-20 1 1- a 0.80 0.60 ref a b c d e f g 9 10 8 11 12 7 5 6 4 2 3 1 bottom view 8.80 sq h j k l m detail a top view detail a coplanarity 0.12 0.50 0.45 0.40 1.70 max ball diameter seating plane 10.10 10.00 sq 9.90 a1 ball corner a1 ball corner 0.32 min 1.00 min ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11536 - 0- 10/13(0)

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